1. Field of the Invention
The invention relates to a field-effect transistor and to a process for fabricating a field-effect transistor.
2. Description of the Related Prior Art
A field-effect transistor of this type and a process for its fabrication are known from [1].
Furthermore, it is known, in the case of the conventional field-effect transistor described in [1], that the length of the space charge region and, by association, the length of the channel region d are indirectly proportional to the root of the doping of the semiconductor used as substrate in the field-effect transistor.
Therefore, the following relationship applies to the field-effect transistors which are known from [1]:                     d        ∝                              1            N                                              (        1        )            
It is clear from this relationship between the length of the channel region and the doping of the substrate that the scalability of a semiconductor component, in particular a semiconductor field-effect transistor, is restricted by the fact that the doping of the semiconductor used can only be scaled to a limited extent.
Furthermore, [2] describes what is known as a metal tunnel transistor, in which a barrier layer, through which electric charge carriers are to tunnel and which according to [2] consists of niobium oxide, is provided between the source region and the drain region of the field-effect transistor.
It is described in [3], [4], that what is known as a field effect can be observed in the metal layer in the case of a very thin metal layer with a thickness of a few nanometers, in particular a thickness of 5.5 nm.
The invention is based on the problem of describing a field-effect transistor and a process for fabricating a field-effect transistor with a scalability which is improved compared to that of the known field-effect transistors.
The problem is solved by the field-effect transistor and the process for fabricating a field-effect transistor having the features described in the independent patent claims.
A field-effect transistor has an electrically nonconductive substrate, a drain region and a source region.
Both the drain region and the source region may contain a metal electrode.
Between the drain region and the source region there is a channel region, the channel region having a metal layer, i.e. A metal layer obviously forms the channel region which is required in a field-effect transistor in order to transfer electrical charge carriers from the source region to the drain region. Furthermore, there is a gate region, by means of which the channel region can be controlled.
A field-effect transistor of this type can be produced using the following process.
A drain region and a source region are formed on or in a substrate. A channel layer, which forms a channel region, is applied to the substrate between the drain region and the source region. A separating layer is applied to the metal layer and between the drain region and the source region. A gate region is formed on the separating layer, the gate region being electrically separated from the drain region, the source region and the channel region by the separating layer, in such a manner that the channel region can be controlled by means of the gate region.
Evidently, the invention can be regarded as consisting in the fact that the channel region, which in conventional field-effect transistors is formed by a semiconductor material and can be controlled by means of a gate region, according to the invention is formed by a metal layer which, on account of a field-effect which occurs with a thin metal layer, can be controlled by means of the gate region of a field-effect transistor.
A second gate region may be provided in the field-effect transistor, so that what is known as a dual gate arrangement is formed in the field-effect transistor. The second gate region can also be used to control the channel region, as in a conventional field-effect transistor. The first gate region and the second gate region may be electrically coupled to one another.
The metal layer may have one or more layers of metal atoms.
Particularly in view of the very high scalability of the metal layer and the fact that the width of the channel region is independent of the doping of the semiconductor material, since metal is now used to produce the channel in the field-effect transistor, the scalability of the field-effect transistor according to the invention is now improved considerably.
A further advantage of the invention is to be seen in particular in the high electrical conductivity of the metal layer which forms the channel region.
In this way, the power loss which is generated when the field-effect transistor switches from a first state into a second state is reduced. On account of the high conductivity of the metal-layer, the speed of the switching operation of the field-effect transistor is also increased considerably compared to conventional field-effect transistors.
The metal layer may contain at least one of the following metals:
platinum, gold, silver, titanium, tantalum, palladium, bismuth, indium, chromium, vanadium, manganese, iron, cobalt, nickel, yttrium, zirconium, niobium, molybdenum, technetium, hafnium, tungsten, or an alloy of at least two of the abovementioned metals.
The separating layer may be an electrically insulating separating layer and/or a layer with a high dielectric constant and/or a ferroelectric layer. In particular, the separating layer may contain SBT, silicon dioxide and/or BST. Furthermore, it is provided, according to a configuration of the invention, for the drain region and/or the source region and/or the gate region to include metal, for example a metal electrode.
The metal used for the metal electrode or the metal electrodes may be the same metals as for the metal layer, i.e. The metal electrode or the metal electrodes may contain:
platinum, gold, silver, titanium, tantalum, palladium, bismuth, indium or an alloy of at least two of the abovementioned metals.
However, it is also possible to use other metals as metal electrodes.
On account of the high conductivity of the corresponding connections, i.e. Electrodes, of the field-effect transistor, the overall conductivity of the field-effect transistor is increased further according to this configuration of the invention, thus increasing the speed when the field-effect transistor switches from a conductive state to a blocking state.
On account of the high switching speed, the field-effect transistor is therefore particularly suitable for high-frequency applications.
The drain region and the source region may be formed on the substrate in a known way, for example by means of predeterminable doping of charge carriers, electrons or holes.
The metal layer may be applied by means of a suitable chemical vapour disposition process (CVD process), a physical vapour deposition process, a sputtering process or an atomic layer deposition process.
The above-described configurations of the invention with regard to the field-effect transistor also apply to the process for fabricating the field-effect transistor.